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Networks-on-Chip [Paperback]

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Item description for Networks-on-Chip by Davide Bertozzi...

Networks-on-Chip by Davide Bertozzi

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Item Specifications...

Studio: Hindawi Publishing Corporation
Pages   152
Est. Packaging Dimensions:   Length: 10.9" Width: 8.3" Height: 0.5"
Weight:   0.95 lbs.
Binding  Softcover
Release Date   Apr 22, 2007
Publisher   Hindawi Publishing Corporation
ISBN  9775945909  
ISBN13  9789775945907  

Availability  0 units.

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Recent research in the emerging technology  Jan 14, 2008
This is an exciting time in computer architecture. Straight-line extensions of the von Neumann programming model are stumbling, while Moore's Law runs on ahead. Supercomputing technologies of the 1980s and 1990s are chip technologies of today, and configurable logic has democratized system-on-chip (SoC) design even as the cost of a chip start has skyrocketed. There, in the middle of these developments, lie networks on the chip. The NoC field is still an expanding research area; there is no standard body of knowledge to fall back on. Instead, practitioners rely on collections of research, such as this set of 2007 papers from the VLSI Design journal.

These papers address a range of topics, all the way down to design for process variation across the width of a chip, current-mode vs. voltage-mode signalling, and other issues of the physical and MAC layers. Higher in the protocol stack, other papers address deadlock avoidance and capacity planning. I found the capacity article especially interesting because the authors convincingly make the case that every SoC has unique demands for latency and bandwidth, so every NoC must be tailored to the application - an important contrast to the one-size-fits-all philosophy that other researchers seem to prefer. I have to agree. Orthogonality of communication and processing sounds nice in theory, but can not be completely separated in practice, and should not be when configurable logic makes customization so straightforward. One thread ties many of these papers together: their concern for fault tolerance. There's no believable chance that every transistor on a billion-transistor chip will be perfect, and shrinking feature sizes make transient upsets a fact of daily life. Systems must tolerate hard and soft failures, so several of these papers address recovery of various kinds.

Very few readers will find every article to be of interest, and beginners won't find a clear roadmap of the basics. Still, anyone involved in NoC development will find something of interest in this set of cutting-edge reports.

-- wiredweird

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